The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit which can be used in general-purpose processors, signal processors, video processors and the like including logic circuits.
Among circuitries using pass-transistors, there have been introduced differential pass-transistor logics as described in IEEE Journal of Solid-state Circuits, Vol.SC-22, No.2, April 1987, pp.216-222 (will be called the first prior art) and complementary pass-transistor logics as described in IEEE Journal of Solid-state Circuits, Vol.SC-25, No.2, April 1990, pp.388-395 (will be called the second prior art). These circuitries are complementary logic circuits using both inverting and non-inverting logics.
Pass-transistor circuits using single-channel MOSFETs, instead of complementary MOSFETs, and a design scheme of pass-transistor circuits of the standard cell scheme are described in Custom Integrated Circuits Conference 1994 Digest, pp.603-606 (will be called the third prior art).
A configuration scheme of pass-transistor circuits based on a logic expression called a binary decision diagram is described in the Proceeding of 1994 Autumn Convention of The Institute of Electronics, Information and Communication Engineers of Japan, edition of fundamentals and interfaces, p.64 (will be called the fourth prior art).
A logical operation scheme based on the binary decision diagram is described in IEEE, Transaction on Computers, Vol.C-35, No.8.August 1986, pp.677-691 (will be called the fifth prior art).
Logic circuits for accomplishing logics of exclusive-OR circuits, full adders and the like based on a scheme of supplying an output signal of a preceding-stage complementary pass-transistor circuit to the gates of complementary MOSFETs of a succeeding-stage complementary transistor circuit are described in Japanese Laid-Open Patent Application No. 1-216622 (will be called the sixth prior art).
Logic circuits for accomplishing logics of exclusive-OR circuits, full adders and the like based on a scheme of supplying an output signal of a preceding-stage complementary pass-transistor circuit to the sources of complementary MOSFETs of a succeeding-stage complementary transistor circuit are described in Japanese Laid-Open Patent Application No. 1-256219 (will be called the seventh prior art).
A parity detection and generation circuit using exclusive-OR circuits based on a scheme of supplying an output signal of a preceding-stage complementary pass-transistor circuit to the gates of complementary MOSFETs of a succeeding-stage complementary transistor circuit and a scheme of supplying a output signal of a preceding-stage complementary pass-transistor circuit to the sources of complementary MOSFETs of the succeeding-stage complementary transistor circuit are described in U.S. Pat. No. 4,477,904 (will be called the eighth prior art).
A pass-transistor circuit requires a smaller number of transistors as compared with a conventional CMOS logic circuit in accomplishing a same logic function, and accordingly the circuit is more suitable for reduced power consumption and delay. However, it is more difficult to synthesize logic circuits comprised of pass-transistor circuits, and therefore they have not been used for random logic circuits which require all logic functions.
The above-mentioned sixth prior art, which adopts a scheme of supplying an output signal of a preceding-stage complementary pass-transistor circuit to the gates of complementary MOSFETs of a succeeding-stage complementary transistor circuit, and the seventh prior art, which adopts a scheme of supplying the output signal of the preceding-stage complementary pass-transistor circuit to the sources of complementary MOSFETs of the succeeding-stage complementary transistor circuit, are both used for logic circuits for accomplishing logics of exclusive-OR circuits, full adders and the like. The sixth and seventh prior arts, however, do not disclose a method for using pass-transistor circuits for accomplishing all logic functions.
The above-mentioned eighth prior art, which adopts both a scheme of supplying an output signal of the preceding-stage complementary pass-transistor circuit to the gates of complementary MOSFETs of the succeeding-stage complementary transistor circuit and a scheme of supplying the output signal of the preceding-stage complementary pass-transistor circuit to the sources of complementary MOSFETs of the succeeding-stage complementary transistor circuit, is applied to parity detection and generation circuits using exclusive-OR circuits. The eighth prior art, however, does not disclose a method for using pass-transistor circuits for accomplishing all logic functions.
It is necessary accomplish intricate logic functions with a smaller number of transistors, if it is intended to provide pass-transistor circuits that can be used for a random logic circuit which requires all logic functions.
The study of the inventors of the present invention revealed that it is difficult for the eighth prior art to accomplish intricate logic functions with a smaller number of transistors, because two MOSFETs of a same conductivity type in the preceding-stage complementary pass-transistor circuit, which drives the gates or sources of complementary MOSFETs of the succeeding-stage pass-transistor circuit, are supplied on their sources with complementary logic signals (high and low).
Accordingly, an object of the present invention is to provide a semiconductor integrated circuit including pass-transistor circuits which require a smaller number of transistors, are suitable for reduction of the power consumption and delay and accomplish intricate logic functions.
In order to achieve the above objective, the semiconductor integrated circuit according to one mode for carrying out the present invention comprises a logic circuit which includes first, second and third pass-transistor circuits (PT1, PT2, PT3). Each pass-transistor circuit has a first input node (In1), a second input node (In2), an output node (Out), a first field effect transistor (will be termed xe2x80x9cFETxe2x80x9d hereinafter) (Q1) having its source-drain path coupled to the first input node (In1) and the output node (Out), and a second PET (Q2) having its source-drain path coupled to the second input node (In2) and the output node (Out). The first FET (Q1) of the second pass-transistor circuit (PT2) has its gate responding to a signal on the output node (Out) of the first pass-transistor circuit (PT1). At least one of the first FET (Q1) and second PET (Q2) of the third pass-transistor circuit (PT3) has its source-drain path coupled to one of the first input node (In1) and output node (Out) of the second pass-transistor circuit (PT2). The first input node (In1) and the second input node (In2) of the first pass-transistor circuit (PT1) are respectively supplied with an input signal and another input signal (B, GND) that are logically independent from each other. See FIGS. 1 and 2.
The semiconductor integrated circuit according to this mode for carrying out the present invention bases the logical decision of the logic circuit output signal, which is obtained on one of the output node of the second pass-transistor circuit and the output node of the third pass-transistor circuit, on (1) a scheme adopted between the first and second pass-transistor circuits, of supplying an output signal of a preceding-stage pass-transistor to a gate of a succeeding-stage pass-transistor, (2) a scheme adopted between the second and third pass-transistor circuits, of supplying an output signal of a preceding-stage pass-transistor to the source-drain path of a succeeding-stage pass-transistor, and (3) a scheme of supplying the input signals that are logically independent from each other to the first and second input nodes of the first pass-transistor circuit.
Thus, the output signal of the logic circuit which includes the first, second and third pass-transistor circuits on these three schemes of applying signals, and therefore, this semiconductor integrated circuit needs a smaller number of transistors and reduced the power consumption and delay and can accomplish intricate logic functions.
Furthermore, a semiconductor integrated circuit which is capable of accomplishing more intricate logic functions can be obtained by changing inter-connection among the first, second and third pass-transistor circuits or by adopting complicated schemes of supplying logical input signals to the first and second input nodes of these pass-transistor circuits.
In the semiconductor integrated circuit according to a specific mode for carrying out the present invention, at least one of the first FET (Q1) and second FET (Q2) of the third pass-transistor circuit (PT3) has its source-drain path coupled to the first input node (In1) of the second pass-transistor circuit (PT2). The first and second FETs (Q1, Q2) of the first pass-transistor circuit (PT1) have their gates responding to first complementary input signals (A, /A) and become conductive in a complementary fashion. The first and second FETs (Q1, Q2) of the second pass-transistor circuit (PT2) have their gates responding to second complementary input signals and become conductive in a complementary fashion. The first and second FETs (Q1, Q2) of the third pass-transistor circuit (PT3) have their gates responding to third complementary input signals (C, /C) and become conductive in a complementary fashion. The first pass-transistor circuit (PT1) produces on its output node (Out) a logical product signal (Axc2x7B) of the first complementary input signals (A, /A) and an input signal (B) received on its first input node (In1). The third pass-transistor circuit (PT3) produces on its output node (Out) a logical product signal (Cxc2x7D) of the third complementary input signals (C, /C) and an input signal (D) received on its first input node (In1). The second pass-transistor circuit (PT2) is supplied with the second complementary input signals derived from the logical product signal (Axc2x7B) produced on the output node (Out) of the first pass-transistor circuit (PT1) and produces on its output node (Out) a synthesis signal (Axc2x7Bxc2x7Cxc2x7D) of a logical product of the logical product signal (Axc2x7B) on the output node (Out) of the first pass-transistor circuit (PT1) and the logical-product signal (Cxc2x7D) on the output node (Out) of the third pass-transistor circuit (PT3). See in FIG. 1.
In a semiconductor integrated circuit according to another specific mode for carrying out the present invention, at least one of the first FET (Q1) and second FET (Q2) of the third pass-transistor circuit (PT3) has its source-drain path coupled to the output node (Out) of the second pass-transistor circuit (PT2). The first and second FETs (Q1, Q2) of the first pass-transistor circuit (PT1) have their gates responding to first complementary input signals (A, /A) and become conductive in a complementary fashion. The first and second FETs (Q1, Q2) of the second pass-transistor circuit (PT2) have their gates responding to second complementary input signals and become conductive in a complementary fashion. The first and second FETs (Q1, Q2) of the third pass-transistor circuit (PT3) have their gates responding to third complementary input signals (D, /D) and become conductive in a complementary fashion. The first pass-transistor circuit (PT1) produces on its output node (Out) a logical-product signal (Axc2x7B) of the first complementary input signals (A, /A) and a first input signal (B) received on its first input node (In1). The second pass-transistor circuit (PT2) is supplied with the second complementary input signals derived from the logical-product signal (Axc2x7B) produced on the output node (Out) of the first pass-transistor circuit (PT1) and produces on its output node (Out) a logical product signal (Axc2x7Bxc2x7C) of the logical-product signal (Axc2x7B) and an input signal C received on its first input node (In1). The third pass-transistor circuit (PT3) is supplied on its first input node (In1) with the logical product signal (Axc2x7Bxc2x7C) from the output node (Out) of the second pass-transistor circuit (PT2) and produces on its output node (Out) a synthesis signal (Axc2x7Bxc2x7Cxc2x7/D) of a logical product of the logical-product signal (Axc2x7Bxc2x7C) provided from the output node (Out) of the second pass-transistor circuit (PT2) and the third complementary input signals (D, /D). See FIG. 2.
In a semiconductor integrated circuit according to a more specific mode for carrying out the present invention, the first and second FETs (Q1, Q2) of each of the first, second and third pass-transistor circuits (PT1, PT2, PT3) are n-channel MOSFETs. The logical-product signal (Axc2x7B) produced on the output node (Out) of the first pass-transistor circuit (PT1) is supplied to the inputs of CMOS inverters (4000, 4002. 4003, 4004) supplied. The second complementary input signals to be supplied to the second pass-transistor circuit (PT2) are produced from the outputs of the CMOS inverters (4000, 4002, 4003, 4004). See FIG. 4.
A semiconductor integrated circuit according to a most specific mode for carrying out the present invention comprises at least two logic circuits (LC1, LC2) having a circuit structure and a logic signal supplying scheme, both similar to those of the logic circuit mentioned above, and a synthesis logic circuit (LC12) which logically processes output signals of the logic circuits (LC1, LC2). See FIGS. 3 and 4.
Other objects and novel features of the present invention will be apparent from the following description of embodiments.